1. Field of the Invention
The present invention relates to a configuration shift register for use in configuring programmable logic devices or other similar devices.
2. Description of Related Art
Programmable logic devices (“PLDs”) (also sometimes referred to as CPLDs, PALs, PLAs, FPLAs, EPLDs, EEPLDs, LCAs, FPGAs, or by other names), are well-known integrated circuits that provide the advantages of fixed integrated circuits with the flexibility of custom integrated circuits. Such devices are well known in the art and typically provide an “off the shelf” device having at least a portion that can be electrically programmed to meet a user's specific needs. Application specific integrated circuits (“ASICs”) have traditionally been fixed integrated circuits, however, it is possible to provide an ASIC that has a portion or portions that are programmable; thus, it is possible for an integrated circuit device to have qualities of both an ASIC and a PLD. The term PLD as used herein will be considered broad enough to not necessarily exclude such devices.
PLDs typically include blocks of logic elements, sometimes referred to as logic array blocks (“LABs”; also referred to by other names, e.g., “configurable logic blocks,” or “CLBs”). Logic elements (“LEs”, also referred to by other names, e.g., “logic cells”) may include a look-up table (LUT) or product term, carry-out chain, register, and other elements. LABs (comprising multiple LEs) may be connected to horizontal and vertical conductors that may or may not extend the length of the PLD's core and connect to input/out (“I/O”) blocks.
I/O blocks include buffers, registers, and may include other elements. I/O blocks (sometimes referred by other labels, e.g., I/O elements, or “IOEs”, I/O buffers, I/O cells, “IOs”, etc.) perform I/O functions that may include, for example, implementing I/O standards (e.g. LVTTL, LVCMOS, 2.5V, 1.8V, etc.) that define the requirements for transmitting/receiving a logical “1” or “0.” I/O functions also may include, for example, buffering data, routing data to and from the various LEs of the PLD, the demultiplexing of signals, and other functions. I/O blocks and other circuitry such as, for example, phase locked loops (PLLs), delay locked loops (DLLs), and other clock circuitry may benefit from being proximate to the periphery and pins of the device.
PLDs have configuration elements that may be reprogrammed. Configuration elements may be realized as RAM bits, flip-flops, EEPROM cells, or other memory elements. Placing new data into the configuration elements programs or reprograms the PLD's logic functions. It is also becoming increasingly desirable to provide programmable I/O blocks that also contain configuration elements.
In some PLDs, the configuration elements are located in a dedicated memory region or regions. In other PLDs, the configuration elements are dispersed throughout the device. In either case, the configuration elements are typically treated together as an addressable array, or grid, that may be programmed with configuration data.
As the quantity of LEs, LABS, I/O blocks, and configuration elements in PLDs grows, the grid of configuration elements can become quite large. Today there is an increasing need for PLDs with a larger number of configuration elements. However, providing a PLD that has a large grid of configuration elements, for example, as large as 2,000×2,000 configuration elements organized in rows and columns, can create time inefficiencies during testing when particular subsets functions of the PLD may need to be repeatedly reprogrammed.
Applying a typical architecture and programming scheme to such a 2,000×2,000 grid of configuration elements would involve connecting the columns (or, alternatively, the rows) of such an array to, for example, a 2,000 row shift register for column-by-column (or alternatively, row-by-row) loading of configuration data into the configuration elements. Specifically, data for a column is loaded serially into a data shift register, and then the configuration data is loaded in parallel into all the rows (or in some instances a subset of all the rows) of a column. To reprogram the entire device, this process is repeated until new data is loaded into all of the configuration elements.
In those PLDs where the I/O blocks are programmable, the configuration elements for the I/O blocks are programmed along with the rest of the configuration elements. Those configuration elements that are relevant to configuration of I/O operations in a PLD would typically be located near the I/O pins which are dispersed around the edge of the PLD. Thus, I/O configuration elements may exist near the top and bottom of many columns across an entire grid of configuration elements. Thus, to reprogram all of the I/O elements, the entire grid of configuration elements must be reprogrammed.
For purposes of regular operation of a PLD by an ultimate end user, it generally does not pose a problem that the entire PLD must be programmed in order to reprogram a particular subset of functions performed by the PLD. Generally the end user would not need to frequently reconfigure the PLD by reprogramming the configuration elements. However, when testing the PLD, it may be necessary to frequently retest the PLD with different configurations. In particular, it may be necessary to frequently reprogram the PLD for purposes of testing the PLD with different configurations of its I/O elements. As the number of configuration elements in a PLD grows, this repeated reprogramming can become increasingly burdensome, particularly when testing multiple PLDs, and particularly given the increasing need to test a PLD with several different configurations of its I/O elements. In addition, it is desirable to be able to reprogram a portion of or the entire periphery of the chip while the core function is left intact. Alternatively, the core could be reprogrammed and the I/O blocks would still be programmed in a specific pattern to allow maintenance of system level functionality.
Therefore, a configuration element organization is needed that will make it possible to reprogram configuration elements relating to a subset of functions, such as, for example, I/O functions, without necessarily reprogramming an entire configuration grid containing other configuration elements not relating to the particular subset of functions. In addition, it is desirable to be able to reprogram a portion of or the entire subset of configuration elements while the grid containing the other configuration elements is left intact. Alternatively, it may be desirable for the grid to be reprogrammed and not the I/O functions, allowing system level functionality to be maintained.